The present invention relates to a semiconductor device and, more particularly, to a semiconductor device including a bipolar transistor and a Bi-CMOS LSI in which the bipolar transistor and a CMOS transistor are mounted on the same chip.
In recent years, a high-performance silicon bipolar transistor technology has increasingly been developed in order to actualize a high-speed and low power consumption LSI, and there has been proposed a technology of constructing a transistor exhibiting high-speed/high frequency characteristics using, a non-selective epitaxial technique.
Furthermore, in recent years, there has been seen a progress of a development of a Bi-CMOS LSI (Bipolar-Complementary Metal Oxide Semiconductor Large Scale Integrated Circuit) which aims at mobile communications technology, etc. Especially, a portable communication terminal is required to be high performance, low power consumption and, in addition, low price, and hence it is a vital question to ensure a product competing strength by thoroughly reducing the costs.
A structure and a method of manufacturing a high-speed silicon bipolar transistor according to the prior art will be explained with reference to FIG. 1.
N-type layers 61 and 64 serving as collectors isolated by element isolation regions 62 and 63 on a p-type silicon substrate 60 containing a high-concentration n-type buried layer (not illustrated), and a silicon single crystal layer 65 which acts as a base region is formed on the collector region 61 and a collector lead-out region 64, and a polycrystalline silicon layer 66 which acts as a base lead-out region is formed on the silicon oxide layers 62 and 63. On the base region 65, an etching stopper film 67 having an opening 83 in the center thereof, and corresponding to the opening, an emitter region 85 is formed in the base region 65. In the peripheral of the etching stopper 67, a base lead-out polysilicon electrode 68 is formed on the base lead-out region 66, and a collector lead-out polysilicon electrode 69 is formed above the external collector lead-out region 64. On the etching stopper film 67, a side wall 82 is formed and the inner surface thereof defines the opening 83. On the polysilicon film 68, a silicon oxide film 70 and a silicon nitride film 80 are formed such that their ends reach the side wall 82, and a polycrystalline film 80 fills the opening 83 from the upper surface of nitride film 80. An insulating inter-layer film 86 is formed on the whole surface, contact holes 88, 89 and 87 are formed respectively corresponding, to the base lead-out region 68, external collector lead-out region 69 and a polysilicon film 84 as an external emitter lead-out region.
Next, a manufacturing method of the above-mentioned conventional high-speed bipolar transistor will be explained with reference to FIG. 1.
First of all, the n-type layers 61, 64 serving as the collector are epitaxially grown on the p-type silicon substrate 60 containing a high-concentration p-type buried layer (not illustrated). Then, through patterning, process of an elementisolation region, an oxide layer depositing process and an etch-back process, an elementisolation of the transistor is effected by the oxide layer 63, and the oxide layer 62 isolates and separates the collector region 61 from the external collector lead-out region 64.
Subsequently, a silicon crystalline layer is grown over the silicon single crystal 65 serving as a base region is grown on the collector region 61, and the polysilicon 60 serving as the base lead-out region is grown the oxide layer 62.
Next, a composite layer consisting of a nitride layer and an oxide layer is deposited over the whole surface, and predetermined patterning is executed on the base region 65, thereby providing the etching stopper layer 67.
Subsequently, there are deposited the polycrystalline silicon 68 and the polycrystalline silicon 69 which respectively serve as a base lead-out region and a collector lead regions. Then, a p-type impurity is ion-implanted into a base electrode, while an n-type impurity is ion-implanted into the collector lead-out region. Further, the oxide layer 70 and the nitride layer 80 are sequentially deposited by a CVD (Chemical Vapor Deposition) method. Thereafter a first opening 71 for forming an emitter region is opened by an RIE (Reactive Ion Etching) method, and simultaneously the base lead-out polysilicon electrode 68 is separated from the collector lead-out polysilicon electrode 69. Thereafter, the oxide layer is deposited by the CVD method, and the side wall spacer 82 is formed by the RIE method. Subsequently, the etching stopper layer 67 is wet-etched so as not to damage the base region 65, thereby forming a second opening 83.
Next, polycrystalline silicon 84 is deposited, an n-type impurity is ion-implanted, and the impurity is diffused in a solid phase within the base region 65 contiguous to the polycrystalline silicon layer 84 by effecting a thermal treatment, thereby providing an emitter region 85. Subsequently, the polycrystalline silicon 84 containing the n-type impurity is subjected to patterning in a predetermined configuration.
Next, an inter-layer insulating film 86 is deposited by the CVD method and, with this serving as an etching mask, after a photo resist has been subjected to the patterning in a predetermined shape by photolithography, the base contact hole 88, the emitter contact hole 87 and collector contact hole 89 are formed by the RIE method. Thereafter, metal wirings are formed by the conventional technique, thus completing the transistor.
In the transistor manufactured by the method described above, an extremely thin base layer can be formed, and hence it is feasible to obtain a higher cut-off frequency than in the transistor having the base layer formed by the conventional ion implanting and diffusion techniques.
There arise, however, the following problems inherent in the bipolar transistor manufactured by the method described above.
To be specific, an electric current flows from an opening 88 to the base lead-out electrode via the polycrystalline silicon 68, the polycrystalline silicon 66 and the single crystal silicon 65 to just under a emitter diffused layer 85 performing a bipolar operation, and therefore a base resistance value increases. Further, a depth of the opening with respect to an emitter opening width, i.e., an aspect ratio, is large, and consequently a base/collector capacity value with respect to an emitter resistance value and an emitter areal size increases. Then high frequency characteristics such as fmax and Ga etc. and noise characteristics such as Nf etc. decline, and besides an emitter plug effect occurs with the result that an emitter base junction can not be obtained well and a yield of the bipolar transistor decreases.
Moreover, the emitter diffused layer width is defined by the side wall spacer formed by the RIE after the emitter opening has been formed, and hence a controllability declines, resulting in such a problem that device characteristics become ununiform.
Further, Bi-CMOS LSI is structured such that a high-performance bipolar transistor and a MOS type field effect transistor are constructed on the same silicon substrate.
A prior art method of manufacturing a semiconductor integrated circuit device components of which are the bipolar transistor as an active element and the MOS type field effect transistor, will be explained with reference to the drawings by way of one example of the LSI discussed above.
To start with, as illustrated in FIG. 2, a thermal oxide layer 203 is provided by thermal oxidation on a silicon substrate 201, and subsequently the oxide layer 203 existing exactly on a region to be formed with an nxe2x88x92 buried layer, is removed by resist patterning based on the photolithography and by an HF series solution. Thereafter, an oxide layer 204 containing antimony (Sb) is deposited on a wafer surface, and the antimony is diffused into the silicon substrate 201 by executing a thermal treatment, thereby providing an nxe2x88x92 buried layer 202.
Next, as shown in FIG. 2, after removing all the oxide layers 203, 204 on the surface by the HF series solution, a single crystal silicon layer 205 containing phosphorus (P) on the order of 3.0xc3x971016/cmxe2x88x923 is grown up to a thickness of approximately 1.0 xcexcm by an epitaxial growth method.
Next, as shown in FIG. 4, after the surface has been oxidated on the order of 500 xc3x85, there are deposited a polysilicon (polycrystalline silicon) 206 having a thickness of approximately 1000 xc3x85 and a silicon nitride layer 207 having a thickness of about 1500 xc3x85, and the resist is subjected to the patterning. Thereafter, the polysilicon and the nitride layer on region which is to be an elementisolation region are removed by the reactive ion etching (RIE).
Next, as shown in FIG. 5, thick oxide layers 208a-208e are formed by thermal oxidation on a region not covered with the nitride layer and used as element isolation oxide layers. Subsequently, the polysilicon 206 and the nitride layer 207 on the wafer surface are removed by CDE (Chemical Dry Etching).
Subsequently, as illustrated in FIG. 6, after the photo resist has been subjected to the patterning, the n-type and p-type impurities are implanted into the MOS transistor forming region, thereby providing an n-well 209 and a p-well 210, respectively.
Thereafter, the oxide layer on the surface of the device region is removed by the HP series solution, and a gate oxide film 211 is formed by the thermal oxidation. Then, polysilicon is deposited on the order of 3000 xc3x85, and gate electrodes 241a, 241b are formed by the resist patterning based on the lithography and by the RIE. Provided further are impurity diffused layers 242a, 242b serving as an nMOS source and an nMOS drain, and impurity diffused layers 243a, 243b serving as a pMOS source and a pMOS drain by the resist patterning based on the lithography and the ion implantation subsequent thereto, thus finishing the CMOS manufacturing process.
Next, as shown in FIG. 7 an oxide layer 271 is deposited on the order of 3000 xc3x85 by an LPCVD (Low Pressure Chemical Vapor Deposition) method, and thereafter the single crystal silicon layer 205 on the region where the bipolar transistor should be manufactured is exposed by the resist patterning based on the lithography and by the etching using the HF series solution.
Next, as illustrated in FIG. 8, a silicon single crystal 245 containing boron (B) on the order of 1.0xc3x971018 cmxe2x88x923 is grown on the region where the single crystal silicon layer 5 is exposed by use of the selective epitaxial technique. Further, the oxide layer is deposited over the entire surface, and the predetermined resist patterning is effected upon the region that should become a base of the bipolar transistor, thus forming an etching stopper layer 248.
Subsequently, as shown in FIG. 9, polysilicon 250 which serve as a base lead-out region and a collector lead-out region is deposited, and, after resist pattern has been carried out, the p-type impurity is ion implanted into the base lead-out region, while the n-type impurity is ion implanted into the collector lead-out region. Furthermore, a nitride layer 261 is deposited by the CVD method. Thereafter, an opening, 255 for providing an emitter region is formed by the RIE.
Subsequently, as illustrated in FIG. 10, the nitride layer is deposited by the CVD method, and the etch-back is effected using the RIE technique, thus providing a side wall spacer 237. Thereafter, the etching, stopper layer 248 is etched by the wet-series etching without causing any damage to the base region, by forming an opening 265 extending to the base region. Furthermore, polysilicon 258 is deposited over the whole surface, and, after arsenic (As) has been ion-implanted, the arsenic is diffused within the base region 252 by executing the thermal treatment, thus providing, an emitter region 256. Thereafter, the photo resist is subjected to the patterning, and the polysilicon 258 containing the n-type impurity is subjected to the patterning by the etching as shown in FIG. 10.
Subsequently, as shown in FIG. 11, an insulating layer 261 on the region, where is to be silicidated, on the collector polysilicon 250 as well as on the base polysilicon, is selectively removed through the resist patterning based on the lithography and the RIE. Thereafter, a refractory metal such as Ti, Co, Ni etc. is deposited thereon, and the thermal treatment is performed, whereby metal silicide 263 is formed on the surfaces of the base polysilicon electrode 250a, the collector polysilicon electrode 250b and the emitter polysilicon electrode 258. The refractory metal which does not yet react is removed by the etching using a sulphuric acid/hydrogen peroxide solution.
Next, the oxide layer is deposited on the order of 8000 xc3x85 by an LPCVD method, thus providing an inter-layer insulating film 272 under a first layer Al wiring layer. Further, as shown in FIG. 12, the inter-layer insulating film 272 is subjected to the patterning by isotropic etching using the photo resist, thereby forming a contact hole 269 to each of electrodes of the MOS type field effect transistors and of the bipolar transistors. Subsequently, a native oxide layer formed on the bottom surface of each contact is removed by an Ar reverse sputtering method, and thereafter a barrier metal such as Ti/TiN etc is deposited by the sputtering method. Moreover, a wiring metal such as Alxe2x80x94Sixe2x80x94Cu etc is deposited by the sputtering method. Thereafter, the resist is subjected to the patterning in a predetermined shape, and the wiring metal is selectively removed by the RIE, thereby providing a wire 275. A desired integrated circuit is thus completed.
The circuit manufactured by the method described above can be used as high-performance Bi-CMOS LSI but presents problems which follow.
Specifically, after the CMOS has been completely formed on the silicon substrate, there is adopted a process of independently constructing the bipolar transistor. Hence, there increases a turn around time (TAT) till a trial product is manufactured since the specifications were determined, and, besides, the manufacturing process becomes complicated, resulting in a rise in the manufacturing costs. Further, when trying to silicidate each of the electrodes of the source, drain and gate in order to enhance CMOS characteristics, it is required that the inter-layer insulating film on the CMOS transistor region be removed. On this occasion, there might be problems, wherein the element isolation oxide layer is reduced and recessed back, and further an etching removal of the insulating layers constituting the bipolar transistor is caused. This leads to a decline of the yield.
Another example of the prior art bipolar transistor is explained with reference to FIG. 13.
In this prior art bipolar transistor, a silicon substrate 381 is provided with device regions 382, 382a which are device isolated by a deep trench element isolation insulating layer 383a. These device regions 382, 382a are separated into a base formation predetermined region 382 and a collector formation predetermined region 382a by a shallow trench element isolation insulating layer 383.
A base epitaxial layer 384 is provided on the base formation predetermined region 382. A polysilicon layer 384a flush with this base epitaxial layer 384 is provided on the insulating layer 383 surrounding the base formation predetermined region 382. Further an epitaxial layer 384b is provided on the collector formation predetermined region 382a. 
An emitter region 392 is provided in a surface region of the base epitaxial layer 384. Further, an insulating layer (known also as an etching stopper layer) having an opening above this emitter region 392, is provided on the base epitaxial layer 384. Then, a base lead-out electrode 386 composed of polysilicon is provided on the base epitaxial layer 384 as well as on the insulating layer 385. The base lead-out electrode 386 has an opening formed above the emitter region 392, and this opening is larger than the opening of the insulating layer 385.
A spacer layer 393 composed of an insulating substance is provided along the side portion of the opening formed in the base lead-out electrode 386.
Further, an emitter electrode 390 formed of the polysilicon, which is, electrically connected to the emitter region 392, is so provided as to fill the opening.
This emitter electrode 390 is electrically insulated from the base lead-out electrode 386 through the spacer layer 393.
On the other hand, a collector electrode 386a composed of the polysilicon is provided on the collector epitaxial layer 384b. 
A refractory metal silicide layer 384 is provided on the surfaces of the base lead-out electrode 386, the collector electrode 386a and the emitter electrode 390, thus reducing a resistance. An inter-layer insulating layer 396 is provided on the base lead-out electrode 386, the collector electrode 386a and the emitter electrode 390. Then, this inter-layer insulating layer 396 is formed with openings as contact holes for coming in contact with the electrodes 386, 386a, 390. Metal electrodes 398a, 398b, 398c each composed of a metal are so provided as to fill these contact holes.
Next, a conventional method of manufacturing the bipolar transistor is described with reference to FIGS. 14A-14I.
To start with, as shown in FIG. 14A, a trench is formed in a silicon substrate 381 and is so embedded with the insulating layer 383 as to effect an elementisolation, and a device region 382 is provided. Next, a singe crystal silicon layer (also called a base epitaxial layer) serving as a base layer is provided on the device region 382 by conducting an epitaxial growth while implanting an impurity of a first conductivity type (of e.g., a p-type), and a polysilicon layer 384a is provided on the element isolation insulating layer 383 (see FIG. 14B). Subsequently, an oxide layer composed of, e.g., SiO2 is deposited on the substrate surface and an etching stopper layer 385 is provided by executing a patterning process (See FIG. 12B).
Next, a polysilicon layer is deposited over the entire surface of the substrate, and subsequently, after a first conductivity type impurity has been implanted into this polysilicon layer, some portions of the polysilicon layer and the polysilicon layer 384a are removed by anisotropic etching (e.g., RIE) (Reactive Ion-Etching)), and the base lead-out electrode 386 formed of the polysilicon is provided (See FIG. 14C).
Next, the oxide layer 387 is deposited over the entire surface of the substrate, and the oxide layer 387 and the base lead-out electrode 386 that are disposed on the region where an emitter is to be provided, are removed by anisotropic etching. Thus, the bottom surface is formed with an opening 388 through which the etching stopper layer 385 is exposed (see FIG. 14D).
Next, a nitride layer is deposited over the entire surface of the substrate, and a side wall layer 389 composed of a nitride is provided along the side portion of the opening 388 by performing the anisotropic etching such as the RIE etc (see FIG. 14E). Subsequently, the etching stopper layer 385 exposed to the bottom surface of the opening 388 is removed by performing the anisotropic etching, thus making the epitaxial layer 384 exposed (see FIG. 14E).
Next, a polysilicon layer 390 is deposited so as to fill the thus formed emitter opening and the opening 388 as ell, and a second conductivity type impurity (of e.g., n-type) is implanted into the polysilicon layer. Thereafter, with a thermal treatment carried out, the second conductivity type impurity is diffused in the surface region of the epitaxial layer 384, thus providing an emitter region 392 (see FIG. 14E). Subsequently, the polysilicon layer 390 is subjected to patterning, thereby providing an emitter electrode 390 (see FIG. 14F).
Next, with the emitter electrode 390 serving as a mask, the anisotropic etching is conducted, and the oxide layer 387 is thus removed (see FIG. 14G). At this time, the oxide layer 387 under the emitter electrode 390 is not removed. This oxide layer 387 not removed and a side all layer 389 form a spacer layer 393 (see FIG. 14G).
A refractory metal (e.g., Ti) is deposited over the whole surface of the substrate by use of a sputtering method, and, with the thermal treatment effected, a silicide layer 394 is provided on the emitter electrode 390 as well as on the base lead-out electrode 386 (see FIG. 14E). With this processing, the base lead-out electrode 386 and the emitter electrode 390 are reduced in terms of their resistances.
Next, as shown in FIG. 14I, an inter-layer insulating layer 396 is deposited over the entire surface of the substrate, and this inter-layer insulating layer 396 is formed with openings serving as contact holes for coming into contact with the base lead-out electrode 386 and the emitter electrode 390, respectively. Then, a metal layer is deposited over the entire surface of the substrate so as to fill these contact holes, and metal electrodes 398a, 398c are provided by executing the patterning on this metal layer, thereby completing the bipolar transistor (see FIG. 14I).
In recent years, a speed-up and a reduction in consumption of the electric power of the bipolar transistor have been demanded and hence there has increasingly been an advancement of scaling in regions of an intrinsic base and an emitter. When reduced in size, however, a rate of an unnecessary parasitic region increased not in the essential part of the bipolar aspect but in the operation of the bipolar transistor. Therefore, a parasitic resistance such as a base resistance and an emitter resistance etc, and a parasitic capacity such as an inter base-collector capacity etc becomes larger than a resistance and capacity of the intrinsic region, which is an obstacle against the speed-up and the reduction in the consumption of the electric power.
In the prior art bipolar transistor described above, it is required that a width of the etching stopper layer 385 be wider extra by an allowance of a side wall 389 thickness plus the opening 388. Therefore, as shown in FIG. 15, the base resistance extremely increases as a portion 399 of the epitaxial layer 384 under the etching stopper layer 385 is widened, resulting in such a problem of causing the obstacle against the speed-up and the reduction in the consumption of the electric power.
Further, if the width dimension of the emitter region 392 is decreased by increasingly making the region hyperfine, an aspect ratio (a ratio of a depth to a width of the opening) of the opening 388 increases, and hence it happens that an impurity concentration of the portion of the emitter electrode 390 which is in contact with the base epitaxial layer 384, is smaller than in other portions. There consequently arises a problem in which a current gain changes depending on the emitter width.
It is a first object of the present invention to provide a semiconductor device capable of restraining a scatter of device characteristics by enhancing high frequency characteristics and noise characteristics of a device and a controllability of an emitter diffused layer width, and of restraining an occurrence of en emitter plug effect
It is a second object of the present invention to provide a high-performance Bi-CMOS LSI at a low cost.
It is a third object of the present invention to provide a semiconductor device which prevent current gain variation in response to the emitter width when scaling is effected.
According to a first aspect of the present invention, there is provided a semiconductor device comprising:
a collector region provided on a surface area of a semiconductor substrate and defined by an elementisolation film,
a base layer provided on said collector region;
an insulating layer having an opening and selectively providing on a first region on a surface of said base layer; and
an emitter layer provided on a surface area of said base layer, corresponding to said opening.
According, to a second aspect of the present invention, there is provided a semiconductor device comprising:
a fist semiconductor region of a second conductivity type provided on a first conductivity type semiconductor substrate, and serving as a collector region, the periphery thereof being defined by a first insulating layer;
a second semiconductor region of a first conductivity type comprising a base region provided on said first semiconductor region and a base lead-out region provided on said first insulating layer;
a second insulating layer having an opening corresponding to an emitter formation predetermined region in said second semiconductor region, and serving as an etching stopper layer provided on said second semiconductor region so that at least a part of peripheral edge of said second semiconductor region is exposed;
an en emitter region of the second conductivity type provided corresponding to said opening on the surface area of said second semiconductor region; and
a metal silicide layer so provided as to be self-aligned with said second insulating layer on the peripheral edge of said second semiconductor region.
In these semiconductor devices, since base polysilicon electrodes are not used as the base lead-out electrode but the metal silicide film is used, the emitter opening can be made shallow resulting, in lowering emitter aspect ratio and further reducing emitter resistance. Moreover, since there exists no side wall spacer if the emitter opening, the emitter aspect ratio is further lowered resulting in further reducing the emitter resistance. Furthermore, base/collector capacitance value per emitter area can be reduced for the degree of no existence of side wall spacer. As a result, high frequency and noise characteristics of bipolar transistors are remarkably enhanced.
According to a third aspect of the present invention, there is provided the semiconductor device comprising:
a bipolar transistor disposed on a first conductivity type epitaxial layer provided on a first region on a semiconductor substrate; and
a CMOS type field effect transistor including a first MIS transistor disposed on a surface area of a second conductivity type first well region provided on a second region on said semiconductor substrate, and a second MIS transistor disposed on a surface area of a first conductivity type second well region provided on a third region on said semiconductor substrate,
wherein said bipolar transistor includes a first conductivity type collector region provided on a surface area of said epitaxial layer, a second conductivity type base region provided on a part of said collector region and a first conductivity type emitter region provided on a part of a surface area of said base region, and
wherein said second MIS transistor includes a source and a drain which are composed of substantially the same impurity and with substantially the same diffusion concentration as those of a part of said base region of said bipolar transistor.
In this semiconductor device, since the same material is commonly used for both of the bipolar transistor portion and the MOS transistor portion, manufacturing process can be simplified. Furthermore, in the bipolar transistor portion, since metal silicide film is formed on the base lead-out electrode, the emitter opening can be made shallow resulting in lowering the emitter aspect ratio and further reducing the emitter resistance and base resistance. As a result, high frequency and low noise characteristics of bipolar transistors are remarkably enhanced.
According to a fourth aspect of the present invention, there is provided a semiconductor device comprising:
a collector region provided on a surface area of a semiconductor substrate and defined by an elementisolation film;
a base layer provided on said collector region;
an insulating layer having an opening on a surface area of said base layer, and provided on said base layer; and
an emitter electrode so provided on said insulating layer as to fill said opening,
wherein said insulating layer is interposed as a single layer between said base layer and said emitter electrode at the periphery of said opening.
In this semiconductor device, since the insulating film below the emitter electrode is made as a single layer, conventional etching stopper film and polysilicon base lead-out are not necessary, as a result high speed operation and low power consumption are achieved due to the reduced base resistance.
According to a fifth aspect of the present invention, there is provided a semiconductor device comprising:
a collector region provided on a surface area of a semiconductor substrate and defined by an elementisolation film;
a base layer provided through an epitaxial growth on the surface of said substrate surrounded by said element isolation film provided on said collector surface area;
an insulating layer having an opening above the surface area of said base layer and provided on said base layer; and
an emitter electrode so provided on said insulating layer as to fill said opening,
wherein said insulating layer is so subjected to patterning as to be self-aligned with said emitter electrode.
In this semiconductor device, since the insulating film of the base layer is patterned by self-aligning manner to the emitter electrode manufacturing process can be simplified.